#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice.h>
#include <cydevice_trm.h>

/* ADC_DelSig_1_Ext_CP_Clk */
#define ADC_DelSig_1_Ext_CP_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define ADC_DelSig_1_Ext_CP_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define ADC_DelSig_1_Ext_CP_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define ADC_DelSig_1_Ext_CP_Clk__CFG2_SRC_SEL_MASK 0x07u
#define ADC_DelSig_1_Ext_CP_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define ADC_DelSig_1_Ext_CP_Clk__PM_ACT_MSK 0x01u
#define ADC_DelSig_1_Ext_CP_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define ADC_DelSig_1_Ext_CP_Clk__PM_STBY_MSK 0x01u

/* ADC_DelSig_1_theACLK */
#define ADC_DelSig_1_theACLK__CFG0 CYREG_CLKDIST_ACFG0_CFG0
#define ADC_DelSig_1_theACLK__CFG1 CYREG_CLKDIST_ACFG0_CFG1
#define ADC_DelSig_1_theACLK__CFG2 CYREG_CLKDIST_ACFG0_CFG2
#define ADC_DelSig_1_theACLK__CFG2_SRC_SEL_MASK 0x07u
#define ADC_DelSig_1_theACLK__CFG3 CYREG_CLKDIST_ACFG0_CFG3
#define ADC_DelSig_1_theACLK__CFG3_PHASE_DLY_MASK 0x0Fu
#define ADC_DelSig_1_theACLK__PM_ACT_CFG CYREG_PM_ACT_CFG1
#define ADC_DelSig_1_theACLK__PM_ACT_MSK 0x01u
#define ADC_DelSig_1_theACLK__PM_STBY_CFG CYREG_PM_STBY_CFG1
#define ADC_DelSig_1_theACLK__PM_STBY_MSK 0x01u

/* ADC_DelSig_1_DSM2 */
#define ADC_DelSig_1_DSM2__BUF0 CYREG_DSM0_BUF0
#define ADC_DelSig_1_DSM2__BUF1 CYREG_DSM0_BUF1
#define ADC_DelSig_1_DSM2__BUF2 CYREG_DSM0_BUF2
#define ADC_DelSig_1_DSM2__BUF3 CYREG_DSM0_BUF3
#define ADC_DelSig_1_DSM2__CLK CYREG_DSM0_CLK
#define ADC_DelSig_1_DSM2__CR0 CYREG_DSM0_CR0
#define ADC_DelSig_1_DSM2__CR1 CYREG_DSM0_CR1
#define ADC_DelSig_1_DSM2__CR10 CYREG_DSM0_CR10
#define ADC_DelSig_1_DSM2__CR11 CYREG_DSM0_CR11
#define ADC_DelSig_1_DSM2__CR12 CYREG_DSM0_CR12
#define ADC_DelSig_1_DSM2__CR13 CYREG_DSM0_CR13
#define ADC_DelSig_1_DSM2__CR14 CYREG_DSM0_CR14
#define ADC_DelSig_1_DSM2__CR15 CYREG_DSM0_CR15
#define ADC_DelSig_1_DSM2__CR16 CYREG_DSM0_CR16
#define ADC_DelSig_1_DSM2__CR17 CYREG_DSM0_CR17
#define ADC_DelSig_1_DSM2__CR2 CYREG_DSM0_CR2
#define ADC_DelSig_1_DSM2__CR3 CYREG_DSM0_CR3
#define ADC_DelSig_1_DSM2__CR4 CYREG_DSM0_CR4
#define ADC_DelSig_1_DSM2__CR5 CYREG_DSM0_CR5
#define ADC_DelSig_1_DSM2__CR6 CYREG_DSM0_CR6
#define ADC_DelSig_1_DSM2__CR7 CYREG_DSM0_CR7
#define ADC_DelSig_1_DSM2__CR8 CYREG_DSM0_CR8
#define ADC_DelSig_1_DSM2__CR9 CYREG_DSM0_CR9
#define ADC_DelSig_1_DSM2__DEM0 CYREG_DSM0_DEM0
#define ADC_DelSig_1_DSM2__DEM1 CYREG_DSM0_DEM1
#define ADC_DelSig_1_DSM2__MISC CYREG_DSM0_MISC
#define ADC_DelSig_1_DSM2__OUT0 CYREG_DSM0_OUT0
#define ADC_DelSig_1_DSM2__OUT1 CYREG_DSM0_OUT1
#define ADC_DelSig_1_DSM2__REF0 CYREG_DSM0_REF0
#define ADC_DelSig_1_DSM2__REF1 CYREG_DSM0_REF1
#define ADC_DelSig_1_DSM2__REF2 CYREG_DSM0_REF2
#define ADC_DelSig_1_DSM2__REF3 CYREG_DSM0_REF3
#define ADC_DelSig_1_DSM2__RSVD1 CYREG_DSM0_RSVD1
#define ADC_DelSig_1_DSM2__SW0 CYREG_DSM0_SW0
#define ADC_DelSig_1_DSM2__SW2 CYREG_DSM0_SW2
#define ADC_DelSig_1_DSM2__SW3 CYREG_DSM0_SW3
#define ADC_DelSig_1_DSM2__SW4 CYREG_DSM0_SW4
#define ADC_DelSig_1_DSM2__SW6 CYREG_DSM0_SW6
#define ADC_DelSig_1_DSM2__TR0 CYREG_NPUMP_DSM_TR0
#define ADC_DelSig_1_DSM2__TST0 CYREG_DSM0_TST0
#define ADC_DelSig_1_DSM2__TST1 CYREG_DSM0_TST1

/* ADC_DelSig_1_DEC */
#define ADC_DelSig_1_DEC__COHER CYREG_DEC_COHER
#define ADC_DelSig_1_DEC__CR CYREG_DEC_CR
#define ADC_DelSig_1_DEC__DR1 CYREG_DEC_DR1
#define ADC_DelSig_1_DEC__DR2 CYREG_DEC_DR2
#define ADC_DelSig_1_DEC__DR2H CYREG_DEC_DR2H
#define ADC_DelSig_1_DEC__GCOR CYREG_DEC_GCOR
#define ADC_DelSig_1_DEC__GCORH CYREG_DEC_GCORH
#define ADC_DelSig_1_DEC__GVAL CYREG_DEC_GVAL
#define ADC_DelSig_1_DEC__OCOR CYREG_DEC_OCOR
#define ADC_DelSig_1_DEC__OCORH CYREG_DEC_OCORH
#define ADC_DelSig_1_DEC__OCORM CYREG_DEC_OCORM
#define ADC_DelSig_1_DEC__OUTSAMP CYREG_DEC_OUTSAMP
#define ADC_DelSig_1_DEC__OUTSAMPH CYREG_DEC_OUTSAMPH
#define ADC_DelSig_1_DEC__OUTSAMPM CYREG_DEC_OUTSAMPM
#define ADC_DelSig_1_DEC__OUTSAMPS CYREG_DEC_OUTSAMPS
#define ADC_DelSig_1_DEC__PM_ACT_CFG CYREG_PM_ACT_CFG10
#define ADC_DelSig_1_DEC__PM_ACT_MSK 0x01u
#define ADC_DelSig_1_DEC__PM_STBY_CFG CYREG_PM_STBY_CFG10
#define ADC_DelSig_1_DEC__PM_STBY_MSK 0x01u
#define ADC_DelSig_1_DEC__SHIFT1 CYREG_DEC_SHIFT1
#define ADC_DelSig_1_DEC__SHIFT2 CYREG_DEC_SHIFT2
#define ADC_DelSig_1_DEC__SR CYREG_DEC_SR
#define ADC_DelSig_1_DEC__TRIM__16H CYREG_FLSHID_CUST_TABLES_DEC_16H
#define ADC_DelSig_1_DEC__TRIM__16L CYREG_FLSHID_CUST_TABLES_DEC_16L
#define ADC_DelSig_1_DEC__TRIM__1H CYREG_FLSHID_CUST_TABLES_DEC_1H
#define ADC_DelSig_1_DEC__TRIM__1L CYREG_FLSHID_CUST_TABLES_DEC_1L
#define ADC_DelSig_1_DEC__TRIM__4H CYREG_FLSHID_CUST_TABLES_DEC_4H
#define ADC_DelSig_1_DEC__TRIM__4L CYREG_FLSHID_CUST_TABLES_DEC_4L
#define ADC_DelSig_1_DEC__TRIM__P25H CYREG_FLSHID_CUST_TABLES_DEC_P25H
#define ADC_DelSig_1_DEC__TRIM__P25L CYREG_FLSHID_CUST_TABLES_DEC_P25L

/* ADC_DelSig_1_IRQ */
#define ADC_DelSig_1_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define ADC_DelSig_1_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define ADC_DelSig_1_IRQ__INTC_MASK 0x20000000u
#define ADC_DelSig_1_IRQ__INTC_NUMBER 29
#define ADC_DelSig_1_IRQ__INTC_PRIOR_NUM 7
#define ADC_DelSig_1_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_29
#define ADC_DelSig_1_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define ADC_DelSig_1_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* Opamp_1_ABuf */
#define Opamp_1_ABuf__CR CYREG_ABUF0_CR
#define Opamp_1_ABuf__MX CYREG_ABUF0_MX
#define Opamp_1_ABuf__NPUMP_ABUF_TR0 CYREG_NPUMP_ABUF_TR0
#define Opamp_1_ABuf__PM_ACT_CFG CYREG_PM_ACT_CFG4
#define Opamp_1_ABuf__PM_ACT_MSK 0x01u
#define Opamp_1_ABuf__PM_STBY_CFG CYREG_PM_STBY_CFG4
#define Opamp_1_ABuf__PM_STBY_MSK 0x01u
#define Opamp_1_ABuf__RSVD CYREG_ABUF0_RSVD
#define Opamp_1_ABuf__SW CYREG_ABUF0_SW
#define Opamp_1_ABuf__TR0 CYREG_ABUF0_TR0
#define Opamp_1_ABuf__TR1 CYREG_ABUF0_TR1

/* Opamp_2_ABuf */
#define Opamp_2_ABuf__CR CYREG_ABUF3_CR
#define Opamp_2_ABuf__MX CYREG_ABUF3_MX
#define Opamp_2_ABuf__NPUMP_ABUF_TR0 CYREG_NPUMP_ABUF_TR0
#define Opamp_2_ABuf__PM_ACT_CFG CYREG_PM_ACT_CFG4
#define Opamp_2_ABuf__PM_ACT_MSK 0x08u
#define Opamp_2_ABuf__PM_STBY_CFG CYREG_PM_STBY_CFG4
#define Opamp_2_ABuf__PM_STBY_MSK 0x08u
#define Opamp_2_ABuf__RSVD CYREG_ABUF3_RSVD
#define Opamp_2_ABuf__SW CYREG_ABUF3_SW
#define Opamp_2_ABuf__TR0 CYREG_ABUF3_TR0
#define Opamp_2_ABuf__TR1 CYREG_ABUF3_TR1

/* SPIS_1_BSPIS */
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__MASK_REG CYREG_B0_UDB12_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_REG CYREG_B0_UDB12_ST
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_REG CYREG_B0_UDB12_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__COUNT_REG CYREG_B0_UDB12_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__PERIOD_REG CYREG_B0_UDB12_MSK
#define SPIS_1_BSPIS_es2_SPISlave_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__3__MASK 0x08u
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__3__POS 3
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__4__MASK 0x10u
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__4__POS 4
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__5__MASK 0x20u
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__5__POS 5
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__6__MASK 0x40u
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__6__POS 6
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__MASK 0x78u
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__MASK_REG CYREG_B0_UDB13_MSK
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_RxStsReg__STATUS_REG CYREG_B0_UDB13_ST
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__0__MASK 0x01u
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__0__POS 0
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__1__MASK 0x02u
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__1__POS 1
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__2__MASK 0x04u
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__2__POS 2
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__6__MASK 0x40u
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__6__POS 6
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__MASK 0x47u
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__MASK_REG CYREG_B0_UDB15_MSK
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_TxStsReg__STATUS_REG CYREG_B0_UDB15_ST
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_A0_REG CYREG_B0_UDB14_15_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_A1_REG CYREG_B0_UDB14_15_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_D0_REG CYREG_B0_UDB14_15_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_D1_REG CYREG_B0_UDB14_15_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_F0_REG CYREG_B0_UDB14_15_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_F1_REG CYREG_B0_UDB14_15_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A0_A1_REG CYREG_B0_UDB14_A0_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A0_REG CYREG_B0_UDB14_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A1_REG CYREG_B0_UDB14_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D0_D1_REG CYREG_B0_UDB14_D0_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D0_REG CYREG_B0_UDB14_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D1_REG CYREG_B0_UDB14_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F0_F1_REG CYREG_B0_UDB14_F0_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F0_REG CYREG_B0_UDB14_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F1_REG CYREG_B0_UDB14_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A0_A1_REG CYREG_B0_UDB15_A0_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A0_REG CYREG_B0_UDB15_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A1_REG CYREG_B0_UDB15_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D0_D1_REG CYREG_B0_UDB15_D0_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D0_REG CYREG_B0_UDB15_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D1_REG CYREG_B0_UDB15_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__DP_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F0_F1_REG CYREG_B0_UDB15_F0_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F0_REG CYREG_B0_UDB15_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F1_REG CYREG_B0_UDB15_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_A0_REG CYREG_B0_UDB12_13_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_A1_REG CYREG_B0_UDB12_13_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_D0_REG CYREG_B0_UDB12_13_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_D1_REG CYREG_B0_UDB12_13_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_F0_REG CYREG_B0_UDB12_13_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_F1_REG CYREG_B0_UDB12_13_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A0_A1_REG CYREG_B0_UDB12_A0_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A0_REG CYREG_B0_UDB12_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A1_REG CYREG_B0_UDB12_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D0_D1_REG CYREG_B0_UDB12_D0_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D0_REG CYREG_B0_UDB12_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D1_REG CYREG_B0_UDB12_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F0_F1_REG CYREG_B0_UDB12_F0_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F0_REG CYREG_B0_UDB12_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F1_REG CYREG_B0_UDB12_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_A0_REG CYREG_B0_UDB13_14_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_A1_REG CYREG_B0_UDB13_14_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_D0_REG CYREG_B0_UDB13_14_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_D1_REG CYREG_B0_UDB13_14_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_F0_REG CYREG_B0_UDB13_14_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_F1_REG CYREG_B0_UDB13_14_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A0_A1_REG CYREG_B0_UDB13_A0_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A0_REG CYREG_B0_UDB13_A0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A1_REG CYREG_B0_UDB13_A1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D0_D1_REG CYREG_B0_UDB13_D0_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D0_REG CYREG_B0_UDB13_D0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D1_REG CYREG_B0_UDB13_D1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F0_F1_REG CYREG_B0_UDB13_F0_F1
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F0_REG CYREG_B0_UDB13_F0
#define SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F1_REG CYREG_B0_UDB13_F1

/* RTC_1_isr */
#define RTC_1_isr__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define RTC_1_isr__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define RTC_1_isr__INTC_MASK 0x200000u
#define RTC_1_isr__INTC_NUMBER 21
#define RTC_1_isr__INTC_PRIOR_NUM 7
#define RTC_1_isr__INTC_PRIOR_REG CYREG_NVIC_PRI_21
#define RTC_1_isr__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define RTC_1_isr__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* CLOCK */
#define CLOCK__0__MASK 0x20u
#define CLOCK__0__PC CYREG_PRT4_PC5
#define CLOCK__0__PORT 4
#define CLOCK__0__SHIFT 5
#define CLOCK__AG CYREG_PRT4_AG
#define CLOCK__AMUX CYREG_PRT4_AMUX
#define CLOCK__BIE CYREG_PRT4_BIE
#define CLOCK__BIT_MASK CYREG_PRT4_BIT_MASK
#define CLOCK__BYP CYREG_PRT4_BYP
#define CLOCK__CTL CYREG_PRT4_CTL
#define CLOCK__DM0 CYREG_PRT4_DM0
#define CLOCK__DM1 CYREG_PRT4_DM1
#define CLOCK__DM2 CYREG_PRT4_DM2
#define CLOCK__DR CYREG_PRT4_DR
#define CLOCK__INP_DIS CYREG_PRT4_INP_DIS
#define CLOCK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define CLOCK__LCD_EN CYREG_PRT4_LCD_EN
#define CLOCK__MASK 0x20u
#define CLOCK__PORT 4
#define CLOCK__PRT CYREG_PRT4_PRT
#define CLOCK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define CLOCK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define CLOCK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define CLOCK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define CLOCK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define CLOCK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define CLOCK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define CLOCK__PS CYREG_PRT4_PS
#define CLOCK__SHIFT 5
#define CLOCK__SLW CYREG_PRT4_SLW

/* MISO */
#define MISO__0__MASK 0x80u
#define MISO__0__PC CYREG_PRT4_PC7
#define MISO__0__PORT 4
#define MISO__0__SHIFT 7
#define MISO__AG CYREG_PRT4_AG
#define MISO__AMUX CYREG_PRT4_AMUX
#define MISO__BIE CYREG_PRT4_BIE
#define MISO__BIT_MASK CYREG_PRT4_BIT_MASK
#define MISO__BYP CYREG_PRT4_BYP
#define MISO__CTL CYREG_PRT4_CTL
#define MISO__DM0 CYREG_PRT4_DM0
#define MISO__DM1 CYREG_PRT4_DM1
#define MISO__DM2 CYREG_PRT4_DM2
#define MISO__DR CYREG_PRT4_DR
#define MISO__INP_DIS CYREG_PRT4_INP_DIS
#define MISO__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define MISO__LCD_EN CYREG_PRT4_LCD_EN
#define MISO__MASK 0x80u
#define MISO__PORT 4
#define MISO__PRT CYREG_PRT4_PRT
#define MISO__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define MISO__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define MISO__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define MISO__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define MISO__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define MISO__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define MISO__PS CYREG_PRT4_PS
#define MISO__SHIFT 7
#define MISO__SLW CYREG_PRT4_SLW

/* MOSI */
#define MOSI__0__MASK 0x10u
#define MOSI__0__PC CYREG_PRT4_PC4
#define MOSI__0__PORT 4
#define MOSI__0__SHIFT 4
#define MOSI__AG CYREG_PRT4_AG
#define MOSI__AMUX CYREG_PRT4_AMUX
#define MOSI__BIE CYREG_PRT4_BIE
#define MOSI__BIT_MASK CYREG_PRT4_BIT_MASK
#define MOSI__BYP CYREG_PRT4_BYP
#define MOSI__CTL CYREG_PRT4_CTL
#define MOSI__DM0 CYREG_PRT4_DM0
#define MOSI__DM1 CYREG_PRT4_DM1
#define MOSI__DM2 CYREG_PRT4_DM2
#define MOSI__DR CYREG_PRT4_DR
#define MOSI__INP_DIS CYREG_PRT4_INP_DIS
#define MOSI__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define MOSI__LCD_EN CYREG_PRT4_LCD_EN
#define MOSI__MASK 0x10u
#define MOSI__PORT 4
#define MOSI__PRT CYREG_PRT4_PRT
#define MOSI__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define MOSI__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define MOSI__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define MOSI__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define MOSI__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define MOSI__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define MOSI__PS CYREG_PRT4_PS
#define MOSI__SHIFT 4
#define MOSI__SLW CYREG_PRT4_SLW

/* SS */
#define SS__0__MASK 0x40u
#define SS__0__PC CYREG_PRT4_PC6
#define SS__0__PORT 4
#define SS__0__SHIFT 6
#define SS__AG CYREG_PRT4_AG
#define SS__AMUX CYREG_PRT4_AMUX
#define SS__BIE CYREG_PRT4_BIE
#define SS__BIT_MASK CYREG_PRT4_BIT_MASK
#define SS__BYP CYREG_PRT4_BYP
#define SS__CTL CYREG_PRT4_CTL
#define SS__DM0 CYREG_PRT4_DM0
#define SS__DM1 CYREG_PRT4_DM1
#define SS__DM2 CYREG_PRT4_DM2
#define SS__DR CYREG_PRT4_DR
#define SS__INP_DIS CYREG_PRT4_INP_DIS
#define SS__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SS__LCD_EN CYREG_PRT4_LCD_EN
#define SS__MASK 0x40u
#define SS__PORT 4
#define SS__PRT CYREG_PRT4_PRT
#define SS__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define SS__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define SS__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define SS__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define SS__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define SS__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define SS__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define SS__PS CYREG_PRT4_PS
#define SS__SHIFT 6
#define SS__SLW CYREG_PRT4_SLW

/* Pin_5 */
#define Pin_5__0__MASK 0x20u
#define Pin_5__0__PC CYREG_PRT15_PC5
#define Pin_5__0__PORT 15
#define Pin_5__0__SHIFT 5
#define Pin_5__AG CYREG_PRT15_AG
#define Pin_5__AMUX CYREG_PRT15_AMUX
#define Pin_5__BIE CYREG_PRT15_BIE
#define Pin_5__BIT_MASK CYREG_PRT15_BIT_MASK
#define Pin_5__BYP CYREG_PRT15_BYP
#define Pin_5__CTL CYREG_PRT15_CTL
#define Pin_5__DM0 CYREG_PRT15_DM0
#define Pin_5__DM1 CYREG_PRT15_DM1
#define Pin_5__DM2 CYREG_PRT15_DM2
#define Pin_5__DR CYREG_PRT15_DR
#define Pin_5__INP_DIS CYREG_PRT15_INP_DIS
#define Pin_5__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Pin_5__LCD_EN CYREG_PRT15_LCD_EN
#define Pin_5__PORT 15
#define Pin_5__PRT CYREG_PRT15_PRT
#define Pin_5__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Pin_5__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Pin_5__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Pin_5__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Pin_5__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Pin_5__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Pin_5__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Pin_5__PS CYREG_PRT15_PS
#define Pin_5__SLW CYREG_PRT15_SLW

/* Pin_6 */
#define Pin_6__0__MASK 0x40u
#define Pin_6__0__PC CYREG_PRT6_PC6
#define Pin_6__0__PORT 6
#define Pin_6__0__SHIFT 6
#define Pin_6__AG CYREG_PRT6_AG
#define Pin_6__AMUX CYREG_PRT6_AMUX
#define Pin_6__BIE CYREG_PRT6_BIE
#define Pin_6__BIT_MASK CYREG_PRT6_BIT_MASK
#define Pin_6__BYP CYREG_PRT6_BYP
#define Pin_6__CTL CYREG_PRT6_CTL
#define Pin_6__DM0 CYREG_PRT6_DM0
#define Pin_6__DM1 CYREG_PRT6_DM1
#define Pin_6__DM2 CYREG_PRT6_DM2
#define Pin_6__DR CYREG_PRT6_DR
#define Pin_6__INP_DIS CYREG_PRT6_INP_DIS
#define Pin_6__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define Pin_6__LCD_EN CYREG_PRT6_LCD_EN
#define Pin_6__PORT 6
#define Pin_6__PRT CYREG_PRT6_PRT
#define Pin_6__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define Pin_6__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define Pin_6__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define Pin_6__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define Pin_6__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define Pin_6__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define Pin_6__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define Pin_6__PS CYREG_PRT6_PS
#define Pin_6__SLW CYREG_PRT6_SLW

/* Pin_7 */
#define Pin_7__0__MASK 0x10u
#define Pin_7__0__PC CYREG_PRT6_PC4
#define Pin_7__0__PORT 6
#define Pin_7__0__SHIFT 4
#define Pin_7__AG CYREG_PRT6_AG
#define Pin_7__AMUX CYREG_PRT6_AMUX
#define Pin_7__BIE CYREG_PRT6_BIE
#define Pin_7__BIT_MASK CYREG_PRT6_BIT_MASK
#define Pin_7__BYP CYREG_PRT6_BYP
#define Pin_7__CTL CYREG_PRT6_CTL
#define Pin_7__DM0 CYREG_PRT6_DM0
#define Pin_7__DM1 CYREG_PRT6_DM1
#define Pin_7__DM2 CYREG_PRT6_DM2
#define Pin_7__DR CYREG_PRT6_DR
#define Pin_7__INP_DIS CYREG_PRT6_INP_DIS
#define Pin_7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define Pin_7__LCD_EN CYREG_PRT6_LCD_EN
#define Pin_7__PORT 6
#define Pin_7__PRT CYREG_PRT6_PRT
#define Pin_7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define Pin_7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define Pin_7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define Pin_7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define Pin_7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define Pin_7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define Pin_7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define Pin_7__PS CYREG_PRT6_PS
#define Pin_7__SLW CYREG_PRT6_SLW

/* Pin_8 */
#define Pin_8__0__MASK 0x04u
#define Pin_8__0__PC CYREG_PRT2_PC2
#define Pin_8__0__PORT 2
#define Pin_8__0__SHIFT 2
#define Pin_8__AG CYREG_PRT2_AG
#define Pin_8__AMUX CYREG_PRT2_AMUX
#define Pin_8__BIE CYREG_PRT2_BIE
#define Pin_8__BIT_MASK CYREG_PRT2_BIT_MASK
#define Pin_8__BYP CYREG_PRT2_BYP
#define Pin_8__CTL CYREG_PRT2_CTL
#define Pin_8__DM0 CYREG_PRT2_DM0
#define Pin_8__DM1 CYREG_PRT2_DM1
#define Pin_8__DM2 CYREG_PRT2_DM2
#define Pin_8__DR CYREG_PRT2_DR
#define Pin_8__INP_DIS CYREG_PRT2_INP_DIS
#define Pin_8__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define Pin_8__LCD_EN CYREG_PRT2_LCD_EN
#define Pin_8__PORT 2
#define Pin_8__PRT CYREG_PRT2_PRT
#define Pin_8__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define Pin_8__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define Pin_8__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define Pin_8__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define Pin_8__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define Pin_8__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define Pin_8__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define Pin_8__PS CYREG_PRT2_PS
#define Pin_8__SLW CYREG_PRT2_SLW

/* Miscellaneous */
/* -- WARNING: define names containting LEOPARD or PANTHER are deprecated and will be removed in a future release */
#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIG_FASTBOOT_ENABLED 0
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
#define CYDEV_CHIP_MEMBER_5A 2
#define CYDEV_CHIP_FAMILY_PSOC5 3
#define CYDEV_CHIP_DIE_PANTHER 2
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PANTHER
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
#define BCLK__BUS_CLK__HZ 24000000U
#define BCLK__BUS_CLK__KHZ 24000U
#define BCLK__BUS_CLK__MHZ 24U
#define CYDEV_APPLICATION_ID 0x0000
#define CYDEV_APPLICATION_VERSION 0x0000
#define CYDEV_BOOTLOADER_CHECKSUM CYDEV_BOOTLOADER_CHECKSUM_BASIC
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
#define CYDEV_BOOTLOADER_FAST_VERIFY 0
#define CYDEV_BOOTLOADER_VERSION 0x0000
#define CYDEV_BOOTLOADER_WAIT_COMMAND 1
#define CYDEV_BOOTLOADER_WAIT_TIME 200
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_DIE_LEOPARD 1
#define CYDEV_CHIP_DIE_UNKNOWN 0
#define CYDEV_CHIP_FAMILY_PSOC3 1
#define CYDEV_CHIP_FAMILY_PSOC4 2
#define CYDEV_CHIP_FAMILY_UNKNOWN 0
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x0E13C069
#define CYDEV_CHIP_MEMBER_3A 1
#define CYDEV_CHIP_MEMBER_UNKNOWN 0
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5A
#define CYDEV_CHIP_REVISION_3A_ES1 0
#define CYDEV_CHIP_REVISION_3A_ES2 1
#define CYDEV_CHIP_REVISION_3A_ES3 3
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
#define CYDEV_CHIP_REVISION_5A_ES0 0
#define CYDEV_CHIP_REVISION_5A_ES1 1
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5A_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PANTHER_PRODUCTION
#define CYDEV_CHIP_REV_LEOPARD_ES1 0
#define CYDEV_CHIP_REV_LEOPARD_ES2 1
#define CYDEV_CHIP_REV_LEOPARD_ES3 3
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
#define CYDEV_CHIP_REV_PANTHER_ES0 0
#define CYDEV_CHIP_REV_PANTHER_ES1 1
#define CYDEV_CONFIGURATION_COMPRESSED 0
#define CYDEV_CONFIGURATION_DMA 1
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_DMA
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CUSTOM_ID 0x00000000
#define CYDEV_DATA_CACHE_ENABLED 0
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_REQXRES 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DEBUG_ENABLE_MASK 0x01
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DBG_DBE
#define CYDEV_DMA_CHANNELS_AVAILABLE 24
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x1000
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_STACK_SIZE 0x4000
#define CYDEV_VDDA 5.0
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5.0
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5.0
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5.0
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5.0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5
#define CYDEV_VIO3_MV 5000
#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
